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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . u l t r a - l o w o n - r e s i s t a n c e , 6 a l o a d s w i t c h w i t h s o f t s t a r t a p l 3 5 2 6 / b 15m w (typical) on-resistance 6a continuous current s o f t s t a r t t i m e p r o g r a m m a b l e b y e x t e r n a l c a p a c i t o r wide input voltage range (vin): 0.8v to 5.5v supply voltage range (vbias): 3v to 5.5v output discharge when switch disabled reverse current blocking when switch disabled over-temperature protection the APL3526/b is an ultra-low on-resistance, power-dis- tribution switch with external soft start control. it integrates a n-channel mosfet that can deliver 6a continuous load current each. the device integrates over-temperature protection. the over temperature protection function shuts down the n- channel mosfet power switch when the junction tem- perature rises beyond 160 o c and will automatically turns on the power switch when the temperature drops by 40 o c. the device is available in lead free tdfn2x2-8 packages. f e a t u r e s g e n e r a l d e s c r i p t i o n a p p l i c a t i o n s notebook aio pc enable input lead free and green devices available (rohs compliant) p i n c o n f i g u r a t i o n s tdfn 2 x 2 - 8 vin 2 7 vout enb 3 bias 4 6 ss 5 gnd 8 vout vin 1 = exposed pad ( connected to ground plane for better heat dissipation ) apl 3526 b ( top view ) tdfn 2 x 2 - 8 vin 2 7 vout en 3 bias 4 6 ss 5 gnd 8 vout vin 1 apl 3526 ( top view ) free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 a p l 3 5 2 6 / b o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v bias bais to gnd voltage - 0.3 ~ 6 v v in vi n to gnd voltage - 0.3 ~ 6 v v out vout to gnd voltage - 0.3 ~ 6 v v en, v enb en or enb to gnd voltage - 0.3 ~ 6 v t j maximum junction temperature - 40 ~ 150 o c t stg storage temperatu re - 65 ~ 150 o c t sdr maximum lead soldering temperature ( 10 seconds ) 26 0 o c note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja junction - to - ambient resistance in free air (note 2) 75 o c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. the exposed pad of tdfn2x2-8 is soldered directly on the pcb. apl 3526 / b package code operating ambient temperature range i : - 40 to 85 o c handling code tr : tape & reel assembly material handling code temperature range package code g : halogen and lead free device assembly material qb : tdfn 2 x 2 - 8 x - date code apl 3526 qb : l 26 x enable function b : active low x - date code apl 3526 b qb : 26 b x enable function blank : active high free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 a p l 3 5 2 6 / b symbol parameter range unit v bias bias input voltage 3.0 ~ 5.5 v v in vin input voltage 0.8 ~ 5.5 v i out vout output current 0 ~ 6 a input logic high 1.2 ~ 5.5 v v en, v enb input logic low 0 ~ 0.4 v t a ambient temperature - 40 ~ 85 o c t j junction tem perature - 40 ~ 125 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) note 3 : refer to the typical application circuit e l e c t r i c a l c h a r a c t e r i s t i c s unless otherwise specified, these specifications apply over v in = 0.8v~5v, v bias =5v, v en =high or v enb =low, and t a = -40~85 o c. typical values are at t a =25 o c. apl3 526/b symbol parameter test conditions min . typ . max . unit supply current bias supply current no load - 50 90 m a bias supply current at shutdown no load, v en =0v or v enb =5v - - 2 m a no load, v bias =5v, v en =0v or v enb =5v, v in =5v - 0.1 8 m a no load, v bias =5v, v en =0v or v enb =5v, v in =3.3v - 0.1 3 m a no load, v bias =5v, v en =0v or v enb =5v, v in =1.8v - 0.1 2 m a vin off - state supply current no load, v bias =5v, v en =0v or v enb =5v, v in =0.8v - 0.1 1 m a reverse leakage current v en =0v or v enb =5v, v in =0v - 0.1 16 m a under - voltage lockout (uvlo) rising bias uvlo threshold v bias rising 1.9 2.4 2.9 v bias uvlo hysteresis - 0.1 - v power switch v bias =5v, v in =0.8~5v, i out =200ma, t j = 2 5 o c - 15 20 m w v bias =5v, v in =0.8~5v, i out =200ma, t j = - 40~ 12 5 o c - - 27 m w v bias =3.3v, v in =0.8~3.3v, i out =200ma, t j = 2 5 o c - 17 23 m w r ds(on) power switch on resistance v bias =3.3v, v in =0.8~3.3v, i out =200ma, t j = - 40~ 12 5 o c - - 31 m w vout discharge resistance v en =0v or v enb =5v , vout force 1v - 1 00 150 w soft - start control pin ss discharge current v ss =6v, v en =0v or v enb =5v , measured at ss - 560 - m a free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 a p l 3 5 2 6 / b e l e c t r i c a l c h a r a c t e r i s t i c s unless otherwise specified, these specifications apply over v in = 0.8v~5v, v bias =5v, v en =high or v enb =low, and t a = -40~85 o c. typical values are at t a =25 o c. apl3 526/b symbol parameter test conditions min . typ . max . unit en or enb input pin input logic high 1.2 - - v v en , v enb input logic low - - 0.4 v input current - - 1 m a overt - temperature protection (otp) over - temperature threshold t j risin g - 160 - c over - temperature threshold hysteresis t j falling - 40 - c p i n d e s c r i p t i o n pin no. name function 1 vin 2 vin power supply input of switch . c onnect this pin to an external dc supply. en enable input of switch. logic high turns on switch. the en pin cannot be left floating . 3 enb enable input of switch. logic low turns on s witch. the enb pin cannot be left floating. 4 bias bias voltage input pin for internal control circuitry. 5 gnd ground pin of the circuitry. all voltage levels are measured with respect to this pin. 6 ss soft start control of switch. a capacitor from th is pin to ground sets the vout ? s rise slew rate. 7 vout 8 vout switch output. exposed pad - connect this pad to system ground plane for good thermal conductivity. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 5 a p l 3 5 2 6 / b b l o c k d i a g r a m uvlo vin vout charge pump en / enb ss bias bulk select control logic otp gnd free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 6 a p l 3 5 2 6 / b t y p i c a l a p p l i c a t i o n c i r c u i t vin vout apl 3526 / b en / enb ss bias gnd 7 , 8 5 6 c ss r load c l 150 m f c out 0 . 1 m f v in c in 1 m f v bias c bias 0 . 1 m f 1 , 2 3 4 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 7 a p l 3 5 2 6 / b f u n c t i o n d e s c r i p t i o n vin under-voltage lockout (uvlo) a under-voltage lockout (uvlo) circuit monitors the vbias pins voltage to prevent wrong logic controls. the uvlo function initiates a soft-start process after the bias sup- ply voltages exceed rising uvlo voltage threshold dur- ing powering on. power switch the power switch is an n-channel mosfet with a ultra- low r ds(on) . when ic is in shutdown state (v en =low or v enb =high), the mosfet prevents a reverse current flow- ing from the vout back to vin. when ic is in uvlo state, the internal parasitic diodes connected from vout to vin will be forward biased. soft-start the APL3526/b provides an adjustable soft-start circuitry to control rise rate of the output voltage and limit the cur- rent surge during start-up. the soft-start time is set with a capacitor from the ss pin to the ground. enable control pulling the enb above 1.2v or en below 0.4v will disable the device, and pulling enb pin below 0.4v or en above 1.2v will enable the device. the en/enb pins cannot be left floating. over-temperature protection (otp) when the junction temperature exceeds 160 o c, the inter- nal thermal sense circuit turns off the power fet and allows the device to cool down. when the device?s junc- tion temperature cools by 40 o c, the internal thermal sense circuit will enable the device, resulting in a pulsed output during continuous thermal protection. thermal protection is designed to protect the ic in the event of over temperature conditions. for normal operation, the junction temperature cannot exceed t j =+125 o c. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 8 a p l 3 5 2 6 / b a p p l i c a t i o n i n f o r m a t i o n power sequencing capacitor selection the APL3526/b requires proper input capacitors to sup- ply current surge during stepping load transients to pre- vent the input voltage rail from dropping. because the parasitic inductor from the voltage sources or other bulk capacitors to the vin pin limit the slew rate of the surge currents, more parasitic inductance needs more input capacitance. for normal applications (except otp or output short cir- cuit has occurred), the recommended input capacitance of vin is 1 m f and output capacitance of vout is 0.1 m f at least. please place the capacitors near the APL3526/b as close as possible. a bulk output capacitor, placed close to the load, is rec- ommended to support load transient current. soft-start capacitor the soft-start capacitor on ss pin can reduce the inrush current and overshoot of output voltage. the capacitor is charge to v ss with a constant 2.5 m a(typ.) current source. this results in a linear charge of the soft-start capacitor and thus the output voltage. the APL3526/b has a built-in reverse current blocking circuit to prevent a reverse current flowing through the body diode of power switch from the vout back vin pin when power switch disabled. the reverse current block- ing circuit is not active before v bias is ready. when ic is in uvlo state, the internal parasitic diodes of power switch connected from vout to vin will be forward biased. otherwise, vout should not be higher than vbias, and vbias must be higher than the voltage of any other input pin, the reason is that the internal parasitic diodes con- nected from vout to vbias will be forward biased. figure 1. APL3526/b power sequencing diagram t h e r m a l c o n s i d e r a t i o n t h e a p l 3 5 2 6 / b m a x i m u m p o w e r d i s s i p a t i o n d e p e n d s o n t h e d i f f e r e n c e s o f t h e t h e r m a l r e s i s t a n c e a n d t e m - p e r a t u r e b e t w e e n j u n c t i o n a n d a m b i e n t a i r . t h e p o w e r d i s s i p a t i o n p d a c r o s s t h e d e v i c e i s : p d = ( t j - t a ) / q j a w h e r e ( t j - t a ) i s t h e t e m p e r a t u r e d i f f e r e n c e b e t w e e n t h e j u n c t i o n a n d a m b i e n t a i r . q j a i s t h e t h e r m a l r e s i s t a n c e b e t w e e n j u n c t i o n a n d a m b i e n t a i r . a s s u m i n g t h e t a = 2 5 c a n d m a x i m u m t j = 1 6 0 c ( t y p i c a l t h e r m a l l i m i t t h r e s h o l d ) , t h e m a x i m u m p o w e r d i s s i p a t i o n i s c a l c u l a t e d a s : p d ( m a x ) = ( 1 6 0 - 2 5 ) / 7 5 = 1 . 8 ( w ) f o r n o r m a l o p e r a t i o n , d o n o t e x c e e d t h e m a x i m u m o p e r - a t i n g j u n c t i o n t e m p e r a t u r e o f t j = 1 2 5 c . t h e c a l c u l a t e d p o w e r d i s s i p a t i o n s h o u l d b e l e s s t h a n : p d = ( 1 2 5 - 2 5 ) / 7 5 = 1 . 3 3 ( w ) p d = ( 1 2 5 - 8 5 ) / 7 5 = 0 . 5 3 ( w ) the power dissipation depends on operating ambient temperature for fixed t j =125 o c and thermal resistance q ja . for APL3526/b packages, the figure 2 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. figure 2. d e r a t i n g c u r v e s f o r a p l 3 5 2 6 / b p a c k a g e 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 1 . 2 1 . 3 1 . 4 - 40 - 30 - 20 - 10 0 10 20 30 40 50 60 70 80 90 ambient temperature ( o c ) p o w e r d i s s i p a t i o n ( w ) v out v in v bias v en v enb v out v in v bias v enb v en free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 9 a p l 3 5 2 6 / b a p p l i c a t i o n i n f o r m a t i o n recommended minimum footprint layout consideration the pcb layout should be carefully performed to maxi- mize thermal dissipation and to minimize voltage drop, droop and emi. the following guidelines must be considered: 1. please place the input capacitors near the vin pin as close as possible. 2. output decoupling capacitors for load must be placed near the load as close as possible for decoupling high frequency ripples. 3. locate APL3526/b and output capacitors near the load to reduce parasitic resistance and inductance for excel- lent load transient performance. 4. the negative pins of the input and output capacitors and the gnd pin must be connected to the ground plane of the load. 5. keep vin and vout traces as wide and short as possible. tdfn2x2-8 0 . 3 0 . 5 0 . 3 0 . 8 0 . 54 1 . 3 the via diameter = 0 . 305 hole size = 0 . 203 unit : mm ground plane for thermal pad free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 0 a p l 3 5 2 6 / b p a c k a g e i n f o r m a t i o n t d f n 2 x 2 - 8 note : 1. follow from jedec mo-229 wccd-3. d e pin 1 dot a b a 1 a 3 nx aaa c seating plane d 2 e 2 l e pin 1 corner k s y m b o l min . max . 0 . 80 0 . 00 0 . 18 0 . 30 1 . 00 1 . 60 0 . 05 0 . 60 a a 1 b d d 2 e e 2 e l millimeters a 3 0 . 20 ref tdfn 2 x 2 - 8 0 . 30 0 . 45 1 . 00 0 . 008 ref min . max . inches 0 . 031 0 . 000 0 . 007 0 . 012 0 . 039 0 . 063 0 . 024 0 . 012 0 . 018 0 . 70 0 . 039 0 . 028 0 . 002 0 . 50 bsc 0 . 020 bsc 1 . 90 2 . 10 0 . 075 0 . 083 1 . 90 2 . 10 0 . 075 0 . 083 k aaa 0 . 20 0 . 08 0 . 003 0 . 008 typ . 0 . 75 0 . 24 1 . 30 0 . 03 0 . 38 0 . 80 2 . 00 2 . 00 typ . 0 . 030 0 . 010 0 . 051 0 . 015 0 . 032 0 . 001 0 . 079 0 . 079 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 1 a p l 3 5 2 6 / b c a r r i e r t a p e & r e e l d i m e n s i o n s a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d application a h t1 c d d w e1 f 178.0 ? 2.00 50 min. 8.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 8.0 ? 0.20 1.75 ? 0.10 3.50 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tdfn2x2 - 8 4.0 ? 0.10 4.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.4 2.35 ? 0.20 2.35 ? 0 .20 1.00 ? 0.20 (mm) d e v i c e s p e r u n i t package type unit quantity tdfn2x2 - 8 tape & reel 3000 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 2 a p l 3 5 2 6 / b t a p i n g d i r e c t i o n i n f o r m a t i o n c l a s s i f i c a t i o n p r o f i l e t d f n 2 x 2 - 8 user direction of feed free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 3 a p l 3 5 2 6 / b c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ tj=125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - a u g . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 4 a p l 3 5 2 6 / b c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 free datasheet http:///

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